DocumentCode
3242144
Title
Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs
Author
Alippi, C. ; Fornaciari, W. ; Pozzi, L. ; Sami, M.
Author_Institution
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
fYear
2001
fDate
2001
Firstpage
50
Lastpage
56
Abstract
Considers reconfigurable computing for application-specific systems, with particular reference to mixed-technology chips. A VLIW “core” is augmented by means of reconfigurable functional units (RFUs) and register files implemented via FPGA on to the same chip. The application is analyzed to extract segments of computation that could be usefully collapsed into complex instructions decoded and executed by the RFUs. In this paper, we focus on the problem of selecting the optimum extension to the native instruction set by means of the “best” segments of the computation that will become complex instructions. In particular, a genetic algorithm approach is introduced to analyze the population of candidates; modifications to the classic genetic operators are introduced to take into account the peculiarity of our problem. Applying the proposed methodology to some significant applications has validated the overall approach
Keywords
field programmable gate arrays; genetic algorithms; instruction sets; mathematical operators; microprocessor chips; mixed analogue-digital integrated circuits; parallel architectures; reconfigurable architectures; FPGA; application-specific reconfigurable VLIW CPU; candidate population analysis; complex instructions; computation segments; genetic algorithm; genetic operators; mixed-technology chips; native instruction set; optimum extended instruction-set architecture; reconfigurable computing; reconfigurable functional units; register files; CMOS technology; Computer architecture; Coprocessors; Data flow computing; Decoding; Field programmable gate arrays; High performance computing; Paper technology; Registers; VLIW;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 12th International Workshop on, 2001.
Conference_Location
Monterey, CA
Print_ISBN
0-7695-1206-2
Type
conf
DOI
10.1109/IWRSP.2001.933838
Filename
933838
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