DocumentCode
3242319
Title
Colif: A multilevel design representation for application-specific multiprocessor system-on-chip design
Author
Cesário, W.O. ; Nicolescu, G. ; Gauthier, L. ; Lyonnard, D. ; Jerraya, A.A.
Author_Institution
TIMA Lab., Grenoble, France
fYear
2001
fDate
2001
Firstpage
110
Lastpage
115
Abstract
Application-specific multiprocessor system-on-chip is required for high-volume future embedded systems. However, obtaining a good application-specific architecture could be an overly complex problem if we consider all the possible customizations. In this paper, we present Colif, a design representation that clearly separates component behavior and communication infrastructure. In addition, it has a flexible communication model that spans multiple abstraction levels. These features are suitable for a design flow where customizing communications and component behaviors at different abstraction levels are the central issue. The paper introduces the main concepts of Colif and compares it to existing system modeling approaches
Keywords
embedded systems; microprocessor chips; multiprocessing systems; parallel architectures; Colif; application-specific multiprocessor system-on-chip design; communication infrastructure; component behavior; design representation; flexible communication model; high-volume future embedded systems; multilevel design representation; multiprocessor system-on-chip; Costs; Embedded system; Energy consumption; Modeling; Multiprocessing systems; Power system reliability; Protocols; System performance; System-on-a-chip; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 12th International Workshop on, 2001.
Conference_Location
Monterey, CA
Print_ISBN
0-7695-1206-2
Type
conf
DOI
10.1109/IWRSP.2001.933847
Filename
933847
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