Charge-up damage of dual gate transistor during RF pre-cleaning of metal contact before barrier metal deposition

Author

Park, Wan-Jae ; Shin, Kyoung-Sub ; Kim, Ji-Soo ; Kang, Chang-Jin ; Ahn, Tae-Hyuk ; Moon, Joo-Tae ; Lee, Moon-Yong

Author_Institution

Semicond. R&D, Samsung Electron. Co. Ltd., Kyungki-Do, South Korea

fYear

1999

fDate

1999

Firstpage

92

Lastpage

95

Abstract

The damage of dual gate (p-gate PMOS and n-gate NMOS) transistors during RF pre-cleaning of their metal contacts before barrier metal deposition has been investigated in logic devices by varying the aspect ratio of metal contacts and RF source power. With higher aspect ratios and a higher source power for RF pre-cleaning, the gate leakage current of PMOS increases, while that of NMOS stays constant. We present a possible explanation for this difference in damage behaviour

Keywords

CMOS logic circuits; MOSFET; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; leakage currents; plasma materials processing; surface charging; surface cleaning; RF pre-cleaning; RF source power; SiO₂-Si; barrier metal deposition; charge-up damage; damage behaviour; dual gate transistor; gate leakage current; logic devices; metal contact; metal contact aspect ratio; metal contacts; n-gate NMOS transistors; p-gate PMOS transistors; Electrodes; Leakage current; Logic devices; MOS devices; Plasma applications; Plasma devices; Plasma immersion ion implantation; Plasma properties; Radio frequency; Sputter etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Plasma Process-Induced Damage, 1999 4th International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-9651577-3-3

Type

conf

DOI

10.1109/PPID.1999.798821

Filename

798821