DocumentCode :
3242468
Title :
A design-for-test technique for multistage analog circuits
Author :
Renovell, M. ; Azais, E. ; Bertrand, Y.
Author_Institution :
Lab. de Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fYear :
1995
fDate :
23-24 Nov 1995
Firstpage :
113
Lastpage :
119
Abstract :
This paper concerns the test of mixed-signal circuits. A novel DFT approach for analog parts constituted of several op-amp-based modules is presented. The idea is to bring the testability resources (controllability and observability) on the frontier of each embedded module by creating transparent paths between external and local I/O´s. The key point of this transformation is to permit each analog stage to have a test mode for which it is converted into a follower stage. Adaptative solutions are proposed depending of the availability of on-chip digital resources eventually re-usable to manage analog test. The testability cost is shown to be very low in terms of additional circuitry, number of extra pins, analog response penalty and test management. A case study is presented that demonstrates the applicability of the method
Keywords :
controllability; design for testability; integrated circuit testing; mixed analogue-digital integrated circuits; observability; production testing; DFT approach; analog response penalty; controllability; design-for-test technique; external I/O; local I/O; mixed-signal circuits; multistage analog circuits; observability; on-chip digital resources; op-amp-based modules; test management; test mode; testability resources; transparent paths; Analog circuits; Availability; Circuit testing; Controllability; Costs; Design for testability; Observability; Operational amplifiers; Pins; Resource management;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
Type :
conf
DOI :
10.1109/ATS.1995.485325
Filename :
485325
Link To Document :
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