EUDOXUS: a WWW-based generator of reusable arithmetic cores

Author

Bakalis, D. ; Adaos, K.D. ; Lymperopoulos, D. ; Alexiou, G.Ph. ; Nikolos, D.

Author_Institution

Dept. of Comput. Eng. & Inf., Patras Univ., Greece

fYear

2001

fDate

2001

Firstpage

182

Lastpage

187

Abstract

Presents a WWW-based tool for the generation of arithmetic soft cores for a wide variety of functions, operand sizes and architectures. The tool produces structural and synthesizable VHDL and/or Verilog descriptions and covers several arithmetic operations, such as addition, subtraction, multiplication, division, squaring, square rooting and shifting. Therefore, designs requiring arithmetic cores, as for example those in digital signal processing and multimedia applications, can be completed faster and with less effort

Keywords

computer architecture; digital arithmetic; digital signal processing chips; hardware description languages; information resources; logic CAD; multimedia computing; software reusability; EUDOXUS; VHDL descriptions; Verilog descriptions; World Wide Web-based tool; addition; arithmetic operations; computer architectures; digital signal processing; division; functions; multimedia applications; multiplication; operand sizes; reusable arithmetic soft core generator; shifting; square rooting; squaring; structural descriptions; subtraction; synthesisable descriptions; Computer architecture; Costs; Digital arithmetic; Electronic mail; Field programmable gate arrays; Hardware design languages; Informatics; Network servers; Productivity; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

Rapid System Prototyping, 12th International Workshop on, 2001.

Conference_Location

Monterey, CA

Print_ISBN

0-7695-1206-2

Type

conf

DOI

10.1109/IWRSP.2001.933858

Filename

933858