Tolerance DC bands of CMOS operational amplifier

Author

Ihs, Hassan ; Dufaza, Christian

Author_Institution

Lab. d´´Inf., de Robotique et de Micro-electron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France

fYear

1995

fDate

23-24 Nov 1995

Firstpage

140

Lastpage

144

Abstract

This paper presents a test technique for CMOS operational amplifier based on the monitoring of some selected DC nodes´ voltages and branches´ currents. A realistic method for determining data tolerance bands due to the foundry process fluctuations of DC branches´ currents and nodes´ voltages of the OA is described. Optimization of the bounds for the fault detection problem is also possible by choosing carefully some design parameters like supply voltage or transistors´ sizes. The efficiency of this technique has been proved by fault simulation when considering a fault model based on catastrophic defects of the transistors´ connections

Keywords

CMOS analogue integrated circuits; circuit optimisation; fault diagnosis; integrated circuit modelling; integrated circuit testing; operational amplifiers; CMOS operational amplifier; DC branch current; DC node voltages; OA; catastrophic defects; data tolerance bands; design parameters; fault detection; fault model; fault simulation; foundry process fluctuations; optimization; supply voltage; tolerance DC bands; transistor connections; transistor size; Analog circuits; Built-in self-test; Circuit faults; Circuit testing; Design optimization; Fault detection; Fluctuations; Monitoring; Operational amplifiers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1995., Proceedings of the Fourth Asian

Conference_Location

Bangalore

Print_ISBN

0-8186-7129-7

Type

conf

DOI

10.1109/ATS.1995.485329

Filename

485329