DocumentCode
3242698
Title
Ultra-thin oxynitride gate dielectrics for 0.18 μm CMOS and beyond
Author
Takayanagi, Mariko ; Toyoshima, Yoshiaki
Author_Institution
ULSI Device Eng. Lab., Toshiba Corp., Yokohama, Japan
fYear
1999
fDate
1999
Firstpage
136
Abstract
Summary form only given. N2O- and/or NO-based oxynitrides are promising candidates for ultra-thin gate dielectrics (<4 nm) in dual-gate CMOS technologies for their superior boron diffusion barrier characteristics. Despite of their importance in the technologies for sub-0.18 μm CMOS generations, systematic studies which correlate interfacial properties with MOSFET characteristics (including reliability issues) have not yet been fully carried out. In this paper, MOSFET characteristics such as Vth variation, I d, μeff and robustness to plasma charging effects are discussed in relation to the interfacial properties of oxynitride gate dielectrics studied by means of TEM, XPS and FT-IR for N 2O and NO oxynitrides ranging between 2-5 nm. It was found that MOSFETs with NO oxynitrides result in superior characteristics, because of the smoother interface and tighter trivalent Si-N bonding at the Si/oxynitride interface
Keywords
CMOS integrated circuits; Fourier transform spectra; MOSFET; X-ray photoelectron spectra; chemical interdiffusion; dielectric thin films; diffusion barriers; integrated circuit measurement; integrated circuit reliability; interface structure; plasma materials processing; silicon compounds; surface charging; transmission electron microscopy; 0.18 micron; 2 to 5 nm; CMOS; FT-IR; MOSFET characteristics; N2O; N2O oxynitrides; N2O-based oxynitrides; NO; NO oxynitrides; NO-based oxynitrides; Si/oxynitride interface; SiON-Si; TEM; XPS; boron diffusion barrier characteristics; dual-gate CMOS technologies; interfacial properties; oxynitride gate dielectrics; plasma charging effects; reliability; smooth interface; threshold voltage variation; trivalent Si-N bonding; ultra-thin gate dielectrics; ultra-thin oxynitride gate dielectrics; Bonding; Boron; CMOS technology; Character generation; Dielectric devices; Laboratories; MOSFET circuits; Plasma properties; Robustness; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Plasma Process-Induced Damage, 1999 4th International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-9651577-3-3
Type
conf
DOI
10.1109/PPID.1999.798832
Filename
798832
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