DocumentCode
3242735
Title
Design and verification driven by assertions
Author
Torres, F. ; Vaca, S. ; Torres, David ; Gonzalez, R.E.
Author_Institution
CTNVESTAV del IPN, Unidad Guadalajara, Zapopan, Jalisco, 45090, Mexico
fYear
2004
fDate
8-10 Sept. 2004
Firstpage
188
Lastpage
193
Abstract
In this paper we propose an improvement of the design cycle of synchronous circuits. The use of semi-formal specifications was necessary to write good code and to perform a formal verification using a model checking tool. Our first results show that the implemented code has several advantages with respect to others written with classical methodologies, and we find that formal and functional verification are complementary.
Keywords
Automatic logic units; Circuit simulation; Cost accounting; Design methodology; Formal verification; Hardware design languages; Logic design; Sequential circuits; Timing; Very high speed integrated circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Electronics Engineering, 2004. (ICEEE). 1st International Conference on
Conference_Location
Acapulco, Mexico
Print_ISBN
0-7803-8531-4
Type
conf
DOI
10.1109/ICEEE.2004.1433874
Filename
1433874
Link To Document