Title :
Generator choices for delay test
Author_Institution :
Power PC Dev. Center, IBM Corp., Austin, TX, USA
Abstract :
An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions on the kind of hardware suitable for the task, especially in built-in self-test applications where the generator must reside on chip. This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. The different options are measured based on their performance, cost, and flexibility
Keywords :
VLSI; automatic testing; boundary scan testing; built-in self test; delays; fault diagnosis; integrated circuit testing; logic testing; shift registers; ATPG; BIST based delay test; cost; delay test vector generator; digital logic circuits; flexibility; generator choices; linear feedback shift register; nonscan designs; performance; pseudo-random test; scan designs; shift dependency; skewed-load delay test; test vectors; timing requirement; transition test; Automatic testing; Built-in self-test; Costs; Delay; Face detection; Fault detection; Hardware; Logic; Semiconductor device measurement; Timing;
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
DOI :
10.1109/ATS.1995.485339
