Identification of robust untestable path delay faults

Author

Wu, Wen Ching ; Lee, Chung Len ; Chen, Jwu E.

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1995

fDate

23-24 Nov 1995

Firstpage

229

Lastpage

235

Abstract

This paper presents a theoretical analysis to identify robust untestable path delay faults. It first classifies the path reconvergence of fanouts into seven cases and deduces the necessary conditions to robustly test path delay faults for each case. It then proposes a procedure, based on the deduced conditions, to identify the robust untestable path delay faults. The procedure was applied to ISCAS 85´ circuits and it was found that the robust untestable faults occupy a high percentage of the total path delay faults. In addition, it also presents a method to estimate the number of robust untestable path delay faults for a circuit

Keywords

automatic testing; combinational circuits; delays; fault diagnosis; logic CAD; logic partitioning; logic testing; multivalued logic; signal flow graphs; ATPG; ISCAS 85´ circuits; ROUNTEST program; combinational circuits; fault identification; partitioning; path reconvergence of fanouts; propagation graph; robust untestable path delay faults; six-valued logic; total path delay faults; Circuit faults; Circuit testing; Delay estimation; Fault diagnosis; Hazards; Logic testing; Manufacturing processes; Propagation delay; Robustness; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1995., Proceedings of the Fourth Asian

Conference_Location

Bangalore

Print_ISBN

0-8186-7129-7

Type

conf

DOI

10.1109/ATS.1995.485341

Filename

485341