Merged Computation for Whirlpool Hashing

Author

Chaves, Ricardo ; Kuzmanov, Georgi ; Sousa, Leonel ; Vassiliadis, Stamatis

Author_Institution

Inst. Super. Tecnico/INESC-ID, Lisbon

fYear

2008

fDate

10-14 March 2008

Firstpage

272

Lastpage

275

Abstract

This paper presents an improved hardware structure for the computation of the Whirlpool hash function. By merging the round key computation with the data compression and by using embedded memories to perform part of the Galois Field (2s) multiplication, a core can be implemented in just 43% of the area of the best current related art while achieving a 12% higher throughput. The proposed core improves the Throughput per Slice compared to the state of the art by 160%, achieving a throughput of 5.47 Gbit/s with 2110 slices and 32 BRAMs on a VIRTEX II Pro FPGA. Results for a real application are also presented by considering a polymorphic computational approach.

Keywords

Galois fields; cryptography; data compression; field programmable gate arrays; BRAMs; Galois field multiplication; VIRTEX II Pro FPGA; Whirlpool hashing; data compression; embedded memories; hardware structure; merged computation; round key computation; Art; Data compression; Embedded computing; Field programmable gate arrays; Galois fields; Hardware; High performance computing; Merging; Testing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2008. DATE '08

Conference_Location

Munich

Print_ISBN

978-3-9810801-3-1

Electronic_ISBN

978-3-9810801-4-8

Type

conf

DOI

10.1109/DATE.2008.4484896

Filename

4484896