A parallel sequential test generation system DESCARTES based on real-valued logic simulation

Author

Date, Hiroshi ; Nakao, Michinobu ; Hatayama, Kazumi

Author_Institution

Res. Lab., Hitachi Ltd., Ibaraki, Japan

fYear

1995

fDate

23-24 Nov 1995

Firstpage

252

Lastpage

258

Abstract

This paper presents a parallel, automatic test generation system, DESCARTES, for synchronous sequential circuits. This system parallelizes the test generation algorithm based on real-valued logic simulation. By addition of a redundant fault identification program and an algorithmic test generation program, test generation is speeded up and test quality is improved. Experimental results for ISCAS ´89 benchmark sequential circuits illustrate the efficiency of this approach

Keywords

VLSI; automatic test software; computational complexity; design for testability; fault diagnosis; logic CAD; logic testing; parallel algorithms; redundancy; sequential circuits; DESCARTES; ISCAS ´89 benchmark sequential circuits; VLSI design; algorithmic test generation program; automatic test generation; concurrent accelerative test generation; distributed processing environment oriented system; parallel sequential test generation system; real-valued logic simulation; redundant fault identification program; stuck-at faults; synchronous sequential circuits; test quality; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Fault diagnosis; Logic testing; Sequential analysis; Sequential circuits; Synchronous generators; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1995., Proceedings of the Fourth Asian

Conference_Location

Bangalore

Print_ISBN

0-8186-7129-7

Type

conf

DOI

10.1109/ATS.1995.485344

Filename

485344