Charging protection and degradation by antenna environment on NMOS and PMOS transistors

Author

Carrere, J.-P. ; Heslinga, D.R.

Author_Institution

Centre Commun, CNET-STMicroelectron.-Philips Semicond., Crolles, France

fYear

1999

fDate

1999

Firstpage

184

Lastpage

187

Abstract

Plasma induced damage from metal etch and HDP oxide deposition are investigated on CMOS structures for different antenna environments. Grounding the antenna environment provides a good protection for NMOS structures against both of these plasma processes, but is inefficient for PMOS structures. We explain this effect by applying electron-shading results to propose a new qualitative injection model

Keywords

CMOS integrated circuits; MOSFET; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; plasma deposition; semiconductor process modelling; sputter etching; CMOS structures; HDP oxide deposition; NMOS structure protection; NMOS transistors; PMOS structures; PMOS transistors; SiO₂-Si; antenna environment; antenna environment grounding; charging degradation; charging protection; electron-shading; metal etch; plasma induced damage; plasma processes; qualitative injection model; Degradation; Electron traps; Etching; MOS devices; MOSFETs; Plasma applications; Plasma measurements; Protection; Testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Plasma Process-Induced Damage, 1999 4th International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-9651577-3-3

Type

conf

DOI

10.1109/PPID.1999.798844

Filename

798844