DocumentCode
3242970
Title
Fault Clustering in deep-submicron CMOS Processes
Author
Schat, Jan
Author_Institution
NXP Semicond., Munich
fYear
2008
fDate
10-14 March 2008
Firstpage
511
Lastpage
514
Abstract
The fraction of ICs that pass all production tests but fail in the application is called the defect level. Defect levels depend on the average number of defects per IC, and also on the clustering of these defects. High clustering leads to a higher yield and a lower defect level. This paper compiles the coefficients for defect clustering using research findings from 1970 until 2001. Because recent data for deep submicron processes are missing in the literature, the clustering coefficient has been calculated using scan fail distributions of ICs in a 180 nm process. Clustering coefficients show a steady trend towards higher defect clustering. This is beneficial, but it is probably not sufficient to achieve today´s ambitious target of ´zero defects´.
Keywords
CMOS integrated circuits; integrated circuit testing; CMOS processes; fault clustering; production tests; scan fail distributions; zero defects; CMOS process; Costs; Fault detection; Fault tolerance; Investments; Machinery; Manufacturing processes; Production; Profitability; Semiconductor device testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2008. DATE '08
Conference_Location
Munich
Print_ISBN
978-3-9810801-3-1
Electronic_ISBN
978-3-9810801-4-8
Type
conf
DOI
10.1109/DATE.2008.4484900
Filename
4484900
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