Title :
Module level weighted random patterns
Author_Institution :
Power PC Dev. Center, IBM Corp., Austin, TX, USA
Abstract :
The paper describes a module level self-test architecture that uses weighted random patterns. A pseudorandom pattern generator (PRPG) is used to generate equally likely patterns that are then transformed to weighted patterns by a universal weighting generator. The module being tested is assumed to be composed of a number of chips all of which have been designed to support a scan test. The signature as collected by a multiple input signature register (MISR). Each scan latch in the module is fed by its near-optimal weight during test. In order to avoid any additional test pins, some of the existing signal pins are designated (demultiplexed) to perform a weight control function during test. This architecture can dramatically decrease the self-test time with only a small increase of hardware overhead
Keywords :
automatic testing; boundary scan testing; integrated circuit testing; logic testing; multivalued logic circuits; probability; module level self-test architecture; multiple input signature register; near-optimal weight; pseudorandom pattern generator; scan latch; scan test; self-test time; signal pins; universal weighting generator; weight control function; weighted random patterns; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Jacobian matrices; Performance evaluation; Pins; System testing; Weight control;
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
DOI :
10.1109/ATS.1995.485347