An analog EPR4 read channel with an FDTS detector

A new read channel architecture is proposed, which uses EPR4 pre-equalization to simplify the hardware required in an all-analog circuit implementation of an FDTS τ=2 detector and its associated timing recovery. The main concept is that by transforming the channel characteristics into an EPR4 target, the FIR filters required in the DFE need only be a few taps long, and the clock may be recovered from the EPR4 pre-equalized data before it enters the DFE. The FDTS τ=2 performance is obtained from a τ=1 implementation, accompanied by an error-pattern identifier. This architecture is designed for high-rate MTR codes, when it outperforms an EPR4 ML read channel at user densities of PW50/T=2 or greater