• DocumentCode
    3243070
  • Title

    Dual threshold voltage circuits in the presence of resistive interconnects

  • Author

    Larsson-Edefors, Per ; Eckerbert, Daniel ; Eriksson, Henrik ; Svensson, Lars J.

  • Author_Institution
    Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
  • fYear
    2003
  • fDate
    20-21 Feb. 2003
  • Firstpage
    225
  • Lastpage
    230
  • Abstract
    We consider the power-optimal design of dual-VT CMOS circuits under challenging delay constraints, with threshold voltages and device sizes as design variables. We show that the presence of interconnect resistance affects the optimum choices of VT and device sizes, and that ignoring the resistance can lead to highly suboptimal results. We also present criteria for deciding when interconnect resistance should be taken into account.
  • Keywords
    CMOS logic circuits; VLSI; circuit optimisation; electric resistance; integrated circuit design; integrated circuit interconnections; logic design; design variables; device sizes; dual threshold voltage circuits; dual-VT CMOS circuits; interconnect resistance; power-optimal design; resistive interconnects; threshold voltages; CMOS logic circuits; CMOS technology; Capacitance; Delay; Driver circuits; Integrated circuit interconnections; Inverters; Logic circuits; Threshold voltage; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
  • Print_ISBN
    0-7695-1904-0
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2003.1183477
  • Filename
    1183477
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3243070