DocumentCode
3243085
Title
Error Floors of LDPC Coded BICM
Author
Ramamoorthy, Aditya ; Varnica, Nedeljko
Author_Institution
Iowa State Univ., Ames
fYear
2007
fDate
24-28 June 2007
Firstpage
839
Lastpage
844
Abstract
In recent years performance prediction for communication systems utilizing iteratively decodable codes has been of considerable interest. There have been significant breakthroughs as far as the analysis of LDPC code ensembles is concerned but the more practical problem of predicting the FER/BER of a particular code has proved to be much more difficult. In this work we present a technique (based on the work of Richardson ´03) for finding lower and upper bounds on the performance of LDPC coded BICM systems for a given code. The insight gained from the prediction technique is used to design interleavers that improve the error floors of these systems.
Keywords
error statistics; interleaved codes; iterative decoding; modulation; parity check codes; BICM systems; FER-BER; LDPC code; bit interleaved coded modulation; communication systems; error floors; iteratively decodable codes; prediction technique; Bit error rate; Communications Society; Computer errors; Error analysis; Iterative decoding; Maximum likelihood decoding; Modulation coding; Parity check codes; Performance analysis; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, 2007. ICC '07. IEEE International Conference on
Conference_Location
Glasgow
Print_ISBN
1-4244-0353-7
Type
conf
DOI
10.1109/ICC.2007.143
Filename
4288814
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