Minimizing Memory Access Schedule for Memories

According to the characteristics of the "3-D" structure of contemporary DRAM chips, the row first column ordered (RFCO) algorithm is proposed in this paper to minimize memory access schedule length. In memory systems with a single memory controller, assuming that the memory access trace is known before scheduling, the RFCO algorithm can generate schedules which are 7.89% shorter than burst scheduling on average. If memory accesses are coming to the single memory controller in real time, the RFCO algorithm can generate schedules which are 8.03% shorter than burst scheduling on average.