• DocumentCode
    3243246
  • Title

    Time-space tradeoffs in the counting hierarchy

  • Author

    Llender, Erica ; KouckÝ, Michal ; Ronnebur, Detlef ; Roy, Sambuddhar ; Vinay, V.

  • Author_Institution
    Dept. of Comput. Sci., Rutgers Univ., Piscataway, NJ, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    295
  • Lastpage
    302
  • Abstract
    Extends the lower-bound techniques of L. Fortnow (2000) to the unbounded-error probabilistic model. A key step in the argument is a generalization of V.A. Nepomnjasˇcˇii˘´s (1970) theorem from the Boolean setting to the arithmetic setting. This generalization is made possible due to the recent discovery of logspace-uniform TC0 circuits for iterated multiplication (A. Chiu et al., 2000). As an example of the sort of lower bounds that we obtain, we show that MAJ-MAJSAT is not contained in PrTiSp(n1+o(1) , nε) for any ε<1. We also extend one of Fortnow´s lower bounds, from showing that S¯A¯T¯ does not have uniform NC1 circuits of size n1+o(1), to a similar result for SAC1 circuits
  • Keywords
    arithmetic; computability; computational complexity; probability; Boolean setting; Nepomnjascii theorem; SAC1 circuits; arithmetic setting; counting hierarchy; iterated multiplication; logspace-uniform TC0 circuits; lower bounds; satisfiability; time-space tradeoffs; unbounded-error probabilistic model; uniform NC1 circuits; Arithmetic; Automation; Binary decision diagrams; Circuits; Complexity theory; Computer science; Polynomials;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computational Complexity, 16th Annual IEEE Conference on, 2001.
  • Conference_Location
    Chicago, IL
  • Print_ISBN
    0-7695-1053-1
  • Type

    conf

  • DOI
    10.1109/CCC.2001.933896
  • Filename
    933896