Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor

Network-on-chip (NoC) is a promising solution for efficient interconnection between processor cores in chip-multi-processor (CMP). This paper is focusing on the energy-efficient design of buffers, a group of the most important components in NoC. From our investigation, an overwhelming majority of "zero" is contained in the packets transmitting in NoC for CMP. A zero-efficient buffer design is proposed as well as the error control scheme. Compared with conventional design, up to 43% energy consumption can be saved. We use a 90 nm CMOS process in our simulation.