Thermal and electro-mechanical challenges in design and operation of high heat flux processors

Many advances in Complementary Metal Oxide Semiconductor (CMOS) technology (deep sub micron feature scales, GHz frequencies, and Silicon On Insulator (SOI)fabrication) have been made possible by increases in the packaging density of electronics. These advances began with the introduction of very large scale integration (VLSI). The combination of increased power dissipation and packaging density led to substantial growth in the chip and system heat fluxes, as well as the amplified complexity in electrical signal integrity and mechanical stackup design in the recent years, particularly in high-end computers. With the trend towards miniaturization, heat removal has become a major bottleneck in product development, especially, in low profile systems, telecom servers and blades. According to ITRS roadmap, power dissipation of high performance single chip packages is predicted to be in 218-288 W range, posing a serious challenge with no proven air-cooled solutions to exist.