High throughput power-aware FIR filter design based on fine-grain pipelining multipliers and adders

In regular FIR structure, by pipelining the multipliers one can improve the throughput. But as with the growth of operand word length, the delay in addition process becomes another important constraint. In this paper, a novel fine-grain pipelining scheme for high throughput FIR is proposed. By pipelining multipliers and adders, very high throughput can be achieved. 2-dimensional pipeline gating technique is used to make the designed FIR power aware of the precision of the operands. The average power dissipation and latency are both significantly reduced with changing of input precisions.