VLSI implementation of SISO arithmetic decoders for joint source channel coding

In this paper we propose an efficient VLSI implementation of a Soft Input Soft Output (SISO) arithmetic code (AC) decoder for joint source channel coding. The addressed application shows a very high level of processing complexity, but, to the best of our knowledge, no papers have been published in the literature on the hardware implementation of the considered joint source channel scheme. First we introduce a simplified algorithm for the SISO AC, which is 1.3 times faster than the standard one. Then an efficient SISO AC architecture is proposed and synthesis results on a 0.13 mum standard cells technology are reported for two different sets of parameters (M=128, M=256). The proposed core runs at 338.9 MHz and can decode up to 124.987 kbit/s.