DocumentCode :
3243338
Title :
Code compression techniques for embedded systems and their effectiveness
Author :
Sundaresan, Krishnan ; Mahapatra, Nihar R.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Buffalo, NY, USA
fYear :
2003
fDate :
20-21 Feb. 2003
Firstpage :
262
Lastpage :
263
Abstract :
Code compression techniques have been used widely in embedded systems to decrease the amount of storage resources needed or to decrease power consumption, and in some cases, to improve performance too. This paper evaluates, using cache models, the performance, power and cost benefits that code compression can provide in an instruction memory hierarchy. It also compares several important code compression schemes on a common platform and using a common set of benchmarks to gauge their effectiveness.
Keywords :
cache storage; data compression; embedded systems; instruction sets; reduced instruction set computing; RISC instruction sets; RISC processor cores; benchmarks; cache models; code compression techniques; embedded systems; instruction memory hierarchy; power consumption; storage resources; Code standards; Computer science; Costs; Embedded system; Energy consumption; Frequency; High level languages; Power engineering and energy; Power system modeling; Reduced instruction set computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-1904-0
Type :
conf
DOI :
10.1109/ISVLSI.2003.1183492
Filename :
1183492
Link To Document :
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