Title :
Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits
Author :
Yoshida, Hiroaki ; Fujita, Masahiro
Author_Institution :
VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo
Abstract :
A continuously-sized circuit resulting from transistor sizing consists of gates with large variety of sizes. In this paper, we first provide a formal formulation of performance-constrained different cell count minimization problem, and then propose an effective hill-climbing heuristic which iteratively minimizes the number of cells under performance constraints such as area, delay and power. To the best of our knowledge, this is the first attempt to address the different cell count minimization problem.
Keywords :
integrated circuit design; logic design; logic gates; minimisation; NOR gates; continuously-sized circuits; design optimization; hill-climbing heuristic; performance-constrained different cell count minimization; transistor sizing; Capacitance; Circuit optimization; Continuing education; Delay effects; Design optimization; Educational technology; Lagrangian functions; Minimization; Timing; Very large scale integration;
Conference_Titel :
Design, Automation and Test in Europe, 2008. DATE '08
Conference_Location :
Munich
Print_ISBN :
978-3-9810801-3-1
Electronic_ISBN :
978-3-9810801-4-8
DOI :
10.1109/DATE.2008.4484924
