Title :
Enhanced techniques for current balanced logic in mixed-signal ICs
Author :
Yang, Li ; Yuan, J.S.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Central Florida Univ., Orlando, FL, USA
Abstract :
In this paper, dual-VT and negative feedback are proposed to reduce the noise of the current-balanced logic for mixed-signal ICs. Based on the circuit analysis and SPICE simulation, the dual-VT technique shows advantages over the conventional current-balanced logic design in gate area, delay, power dissipation, and switching noise. The negative feedback further reduces the noise spike.
Keywords :
SPICE; circuit feedback; integrated circuit design; integrated circuit noise; integrated logic circuits; logic design; mixed analogue-digital integrated circuits; SPICE simulation; circuit analysis; current balanced logic; delay; dual-VT technique; gate area; mixed-signal IC design; negative feedback; power dissipation; switching noise; Analytical models; Circuit analysis; Circuit noise; Circuit simulation; Delay; Logic design; Negative feedback; Noise reduction; Power dissipation; SPICE;
Conference_Titel :
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-1904-0
DOI :
10.1109/ISVLSI.2003.1183499
