Title :
Mini-threads: increasing TLP on small-scale SMT processors
Author :
Redstone, Joshua ; Eggers, Susan ; Levy, Henry
Author_Institution :
Washington Univ., St. Louis, MO, USA
Abstract :
Several manufacturers have recently announced the first simultaneous-multithreaded processors, both as single CPU and as components of multi-CPU chips. All are small scale, comprising only two to four thread contexts. A significant impediment to the construction of larger-scale SMT is the register file size required by a large number of contexts. This paper introduces and evaluates mini-threads, a simple extension to SMT that increases thread-level parallelism without the commensurate increase in register file size. A mini-threaded SMT CPU adds additional per-thread state to each hardware context; an application executing in a context can create mini-threads that will utilize its own per-thread state, but share the context´s architectural register set. The resulting performance will depend on the benefits of additional TLP compared to the costs of executing mini-threads with fewer registers. Our results quantify these factors in detail and demonstrate that mini-threads can improve performance significantly, particularly on small-scale, space-sensitive CPU designs.
Keywords :
microprocessor chips; multi-threading; parallel architectures; performance evaluation; TLP; architectural register set; mini-threads; multi-CPU chips; performance; register file size; simultaneous-multithreaded processors; small-scale SMT processors; thread-level parallelism; Application software; Hardware; Impedance; Manufacturing processes; Parallel processing; Pipelines; Registers; Surface-mount technology; Throughput; Yarn;
Conference_Titel :
High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on
Print_ISBN :
0-7695-1871-0
DOI :
10.1109/HPCA.2003.1183521