DocumentCode :
3243972
Title :
A fine-grain multithreading superscalar architecture
Author :
Loikkanen, Mat ; Bagherzadeh, Nader
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
fYear :
1996
fDate :
35339
Firstpage :
163
Lastpage :
168
Abstract :
In this study we show that fine-grain multithreading is an effective way to increase instruction-level parallelism and hide the latencies of long-latency operations in a superscalar processor. The effects of long-latency operations, such as remote memory references, cache-misses, and multi-cycle floating-point calculations, are detrimental to performance since such operations typically cause a stall. Even superscalar processors, that are capable of performing various operations in parallel, are vulnerable. A fine-grain multithreading paradigm and unique multithreaded superscalar architecture is presented. Simulation results show significant speedup over single-threaded superscalar execution
Keywords :
multiprocessing systems; parallel architectures; fine-grain; instruction-level parallelism; multithreaded superscalar architecture; multithreading; superscalar architecture; superscalar processor; Computational modeling; Computer architecture; Computer science; Computer simulation; Delay; Multithreading; Operating systems; Parallel processing; Processor scheduling; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques, 1996., Proceedings of the 1996 Conference on
Conference_Location :
Boston, MA
ISSN :
1089-795X
Print_ISBN :
0-8186-7633-7
Type :
conf
DOI :
10.1109/PACT.1996.552663
Filename :
552663
Link To Document :
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