Minimizing the effects of tolerance faults on hardware realizations of cellular neural networks

Author

Tetzlaff, Ronald ; Kunz, R. ; Geis, G. ; Wolf, D.

Author_Institution

Inst. fur Angewandte Phys., Frankfurt Univ., Germany

fYear

1998

fDate

14-17 Apr 1998

Firstpage

385

Lastpage

390

Abstract

In this paper a procedure for minimizing the effects of tolerance faults in cellular neural network (CNN) chips is presented. The simulation system SCNN was connected with the “CNN prototyping system” for adjusting the parameter values of the cp300 CNN chip. Results showing the erroneous outputs of the VLSI chip are presented, together with a suitable way for adapting parameter directly to a CNN realization

Keywords

VLSI; analogue processing circuits; cellular neural nets; error analysis; fault tolerant computing; image processing; minimisation; neural chips; VLSI; cellular neural networks; cp300 analogue CNN chip; error minimisation; hardware realizations; image processing; neural net chips; prototyping system; simulation; tolerance faults; Backpropagation algorithms; Cellular neural networks; Circuit faults; Equations; Joining processes; Linux; Minimization methods; Neural network hardware; Very large scale integration; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Cellular Neural Networks and Their Applications Proceedings, 1998 Fifth IEEE International Workshop on

Conference_Location

London

Print_ISBN

0-7803-4867-2

Type

conf

DOI

10.1109/CNNA.1998.685407

Filename

685407