• DocumentCode
    3244081
  • Title

    Dynamic voltage scaling with links for power optimization of interconnection networks

  • Author

    Shang, Li ; Peh, Li-Shiuan ; Jha, Niraj K.

  • Author_Institution
    Dept. of Electr. Eng., Princeton Univ., NJ, USA
  • fYear
    2003
  • fDate
    8-12 Feb. 2003
  • Firstpage
    91
  • Lastpage
    102
  • Abstract
    Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these networks get deployed in a wide range of new applications, where power is becoming a key design constraint, we need to seriously consider power efficiency in designing interconnection networks. As the demand for network bandwidth increases, communication links, already a significant consumer of power now, will take up an ever larger portion of total system power budget. In this paper we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS policy that judiciously adjusts link frequencies and voltages based on past utilization. Our approach realizes up to 6.3× power savings (4.6× on average). This is accompanied by a moderate impact on performance (15.2% increase in average latency before network saturation and 2.5% reduction in throughput.) To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks.
  • Keywords
    delays; frequency control; multiprocessor interconnection networks; performance evaluation; power consumption; voltage control; average latency; communication links; dynamic voltage scaling; frequency adjustment; history-based DVS policy; interconnection networks; network saturation; performance; power consumption minimization; power efficiency; power optimization; throughput reduction; Bandwidth; Circuits; Dynamic voltage scaling; Fabrics; Frequency; IP networks; Microprocessors; Multiprocessing systems; Multiprocessor interconnection networks; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on
  • ISSN
    1530-0897
  • Print_ISBN
    0-7695-1871-0
  • Type

    conf

  • DOI
    10.1109/HPCA.2003.1183527
  • Filename
    1183527