DocumentCode
3244290
Title
Tradeoffs in buffering memory state for thread-level speculation in multiprocessors
Author
Garzaran, Maria Jesus ; Prvulovic, Milos ; Llabería, José María ; Vinals, Victor ; Rauchwerger, Lawrence ; Torrellas, Josep
Author_Institution
Zaragoza Univ., Spain
fYear
2003
fDate
8-12 Feb. 2003
Firstpage
191
Lastpage
202
Abstract
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or speculative memory state that needs to be separately buffered and managed in the presence of distributed caches and buffers. Such state may contain multiple versions of the same variable. In this paper, we introduce a novel taxonomy of approaches to buffering and managing multi-version speculative memory state in multiprocessors. We also present a detailed complexity-benefit tradeoff analysis of the different approaches. Finally, we use numerical applications to evaluate the performance of the approaches under a single architectural framework. Our key insights are that support for buffering the state of multiple speculative tasks and versions per processor is more complexity-effective than support for merging the state of tasks with main memory lazily. Moreover, both supports can be gainfully combined and, in large machines, their effect is nearly fully additive. Finally, the more complex support for future state in main memory can boost performance when buffers are under pressure, but hurts performance when squashes are frequent.
Keywords
cache storage; multi-threading; multiprocessing systems; parallel architectures; performance evaluation; architectural support; buffering memory state; complexity-benefit tradeoff analysis; distributed caches; hard-to-analyze code; multi-version speculative memory state; multiple variable versions; multiprocessors; parallel code; performance evaluation; taxonomy; thread-level speculation; Memory management; Merging; Pollution; Proposals; Taxonomy;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on
ISSN
1530-0897
Print_ISBN
0-7695-1871-0
Type
conf
DOI
10.1109/HPCA.2003.1183537
Filename
1183537
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