• DocumentCode
    3244433
  • Title

    Caches and hash trees for efficient memory integrity verification

  • Author

    Gassend, Blaise ; Suh, G. Edward ; Clarke, Dwaine ; Van Dijk, Marten ; Devadas, Srinivas

  • Author_Institution
    Lab. for Comput. Sci., MIT, Cambridge, MA, USA
  • fYear
    2003
  • fDate
    8-12 Feb. 2003
  • Firstpage
    295
  • Lastpage
    306
  • Abstract
    We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified program execution. A number of schemes are presented with different levels of integration between the on-processor L2 cache and the hash-tree machinery. Simulations show that for the best of our methods, the performance overhead is less than 25%, a significant decrease from the 10× overhead of a naive implementation.
  • Keywords
    cache storage; memory architecture; performance evaluation; tree data structures; certified program execution; hardware cost; hash trees; high performance processor; memory integrity verification; on-processor L2 cache; untrusted external memory; Application software; Bandwidth; Computer science; Coprocessors; Costs; Hardware; Laboratories; Machinery; Protection; Security;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on
  • ISSN
    1530-0897
  • Print_ISBN
    0-7695-1871-0
  • Type

    conf

  • DOI
    10.1109/HPCA.2003.1183547
  • Filename
    1183547