DocumentCode :
3244515
Title :
Cost-sensitive cache replacement algorithms
Author :
Jeong, Jaeheon ; Dubois, Michel
Author_Institution :
IBM Corp., Research Triangle Park, NC, USA
fYear :
2003
fDate :
8-12 Feb. 2003
Firstpage :
327
Lastpage :
337
Abstract :
Cache replacement algorithms originally developed in the context of simple uniprocessor systems aim to reduce the miss count. However, in modern systems, cache misses have different costs. The cost may be latency, penalty, power consumption, bandwidth consumption, or any other ad-hoc numerical property attached to a miss. In many practical situations, it is desirable to inject the cost of a miss into the replacement policy. In this paper, we propose several extensions of LRU which account for nonuniform miss costs. These LRU extensions have simple implementations, yet they are very effective in various situations. We first explore the simple case of two static miss costs using trace-driven simulations to understand when cost-sensitive replacements are effective. We show that very large improvements of the cost function are possible in many practical cases. As an example of their effectiveness, we apply the algorithms to the second-level cache of a multiprocessor with superscalar processors, using the miss latency as the cost function. By applying our simple replacement policies sensitive to the latency of misses we can improve the execution time of some parallel applications by up to 18%.
Keywords :
cache storage; delays; multiprocessing systems; parallel architectures; performance evaluation; LRU extensions; cache misses; cost function; cost-sensitive cache replacement algorithms; execution time; miss latency; multiprocessor; nonuniform miss costs; parallel applications; second-level cache; static miss costs; superscalar processors; trace-driven simulations; Aggregates; Bandwidth; Computer architecture; Cost function; Delay; Energy consumption; Heuristic algorithms; Multiprocessing systems; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on
ISSN :
1530-0897
Print_ISBN :
0-7695-1871-0
Type :
conf
DOI :
10.1109/HPCA.2003.1183550
Filename :
1183550
Link To Document :
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