Supporting the memory system evaluation with a monitor simulator

The memory system is one of the most important issues which exhibit a critical impact on the performance of applications running on both uni- and multi-processors. This paper presents a simulation approach capable of collecting detailed information about the complete memory hierarchy, providing thereby feedback that can support explicit optimizations as well as automatic tuning of programs with respect to memory efficiency. The deployed simulator is a flexible and independent component modeling an existing hardware monitor which observes the inter-node communications. The monitor simulator is also capable of tracing the transactions within a single processor In addition, it can be optionally combined with any level of the entire memory system and used in combination with various simulation tools. This allows a collection of accurate and comprehensive performance data, while keeping the monitoring component extensible, portable, and well applicable.