A compensation technique using floating gate transistors

This paper presents a novel compensation technique for two-staged amplifiers using floating gate transistors. The proposed technique does not use a Miller capacitor, but the dominant pole is compensated by introducing a zero in the left half plane. As a result, the bandwidth is extended by a factor of the second stage gain. A DC gain of IOdB, a GB product of 230 MHz and a phase margin of 63° were obtained; with a single 3.3 V power supply. Simulation results were obtained using a BSIM3, level 49 model, for 0.5/ spl um/ technology parameters through MOSIS.