The design of parallelized BCH codec

Based on the characteristics of Flash memory, this paper introduces a parallel linear feedback shift register to implement the coder and parallel Chien search circuit to make up the decoder. The BM algorithm, using Newton´s equation, is used to get the error location polynomial, thus making it possible to get error location by Chien search. The parallel BCH codec discussed in this paper has advantage in higher error-correcting capability and can be configured for three different error-correcting capabilities. So it can be used many situations. In addition, shorted code is choosed to speed up Chien search progresses in this paper. At last, the decode speed and the error probability is analyzed. The whole design has been realized and verified with Verilog HDL.