RTL verification strategies

If software studies were applied to ASIC designs using VHDL or Verilog code, we could expect about one to three errors per hundred lines of code. Finding errors accounts for approximately fifty percent of project labor costs. Available verification approaches are testing, design reviews/code inspections, prototype/emulation, requirements tracing, and formal verification. Verification occurs throughout the design flow and should occur at various levels of integration. This paper discusses a strategy of module/unit testing, integration testing, system testing, and regression testing. It describes four test approaches (functional, structural, error-oriented and stress/performance)