RTL power management

Author

Toomajanian, Garo

Author_Institution

Sente Inc., Acton, MA, USA

fYear

1998

fDate

15-17 Sep 1998

Firstpage

139

Lastpage

146

Abstract

Integrated circuit (IC) designers who believe their competence is in developing the architecture, and not the implementation, are looking to register transfer level (RTL) sign-off as a means of getting system-on-a-chip (SOC) ICs to market quickly. In order to create complex SOC designs with strict performance, power, and cost constraints, designers must utilize high-level floorplanning, timing analysis, and power estimation tools to achieve their goals. This paper shows how high-level power estimation and analysis tools help SOC designers reduce packaging costs, improve reliability, and increase battery life

Keywords

CMOS integrated circuits; application specific integrated circuits; circuit CAD; circuit analysis computing; circuit optimisation; high level synthesis; integrated circuit design; ASIC design; IC power analysis tools; RTL power management; battery life; high-level power estimation; high-level synthesis; packaging costs reduction; power constraints; register transfer level; reliability improvement; system-on-a-chip design; Batteries; Costs; Energy management; Life estimation; Packaging; Performance analysis; Power system management; Registers; System-on-a-chip; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Wescon/98

Conference_Location

Anaheim, CA

ISSN

1095-791X

Print_ISBN

0-7803-5078-2

Type

conf

DOI

10.1109/WESCON.1998.716436

Filename

716436