Small fan-in is beautiful

Author

Beiu, Valeriu ; Makaruk, Hanna E.

Author_Institution

Space & Atmos. Div., Los Alamos Nat. Lab., NM, USA

Volume

2

fYear

1998

fDate

4-9 May 1998

Firstpage

1321

Abstract

The starting points of this paper are two size-optimal solutions: (i) one for implementing arbitrary Boolean functions; and (ii) another one for implementing certain sub-classes of Boolean functions. Because VLSI implementations do not cope well with highly interconnected nets-the area of a chip grows with the cube of the fan-in-this paper analyses the influence of limited fan-in on the size optimality for the two solutions mentioned. First, we extend one result from Horne and Hush (1994) valid for fan-in Δ=2 to arbitrary fan-in. Second, we prove that size-optimal solutions are obtained for small constant fan-ins for both constructions, while relative minimum size solutions can be obtained for fan-ins strictly lower than linear. These results are in agreement with similar ones proving that for small constant fan-ins (Δ=6...9) there exist VLSI-optimal (i.e., minimising AT²) solutions, while there are similar small constants relating to our capacity of processing information

Keywords

Boolean functions; VLSI; feedforward neural nets; neural chips; Boolean functions; VLSI implementations; relative minimum size solutions; size-optimal solutions; small fan-in; Boolean functions; Capacitance; Delay; Feedforward neural networks; LAN interconnection; Laboratories; Neural networks; Neurons; Vectors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks Proceedings, 1998. IEEE World Congress on Computational Intelligence. The 1998 IEEE International Joint Conference on

Conference_Location

Anchorage, AK

ISSN

1098-7576

Print_ISBN

0-7803-4859-1

Type

conf

DOI

10.1109/IJCNN.1998.685966

Filename

685966