Digital calibration technique for A 14-bit 125-MS/s pipelined ADC using PN dithering

This paper presents a new scheme of digital calibration for a 14-bit 125-MS/s pipelined ADC. The proposed digital calibration corrects the linearity errors resulted from capacitor mismatches, finite Operational Transconductance Amplifier (OTA) gain and OTA´s settling error. This calibration method is based on radix-based calibration, and Pseudo-random Noise (PN) sequence is injected into the Multiplying DAC (MDAC) to extract the equivalent radix. According to the calibration system, simulation results show that when the prototype ADC is sampled at 125 MS/s, the Spurious Free Dynamic Range (SFDR) improves from 51.64 dB to 102.27 dB with calibration, and the Signal to Noise and Distortion Ratio (SNDR) improves from 36.47 dB to 80.86 dB with calibration.