Digital calibration technique for A 14-bit 125-MS/s pipelined ADC using PN dithering

Author

Fan, Kai ; Xiaoming Liu ; Lee, Alex

Author_Institution

Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China

fYear

2011

fDate

7-9 Dec. 2011

Firstpage

1

Lastpage

4

Abstract

This paper presents a new scheme of digital calibration for a 14-bit 125-MS/s pipelined ADC. The proposed digital calibration corrects the linearity errors resulted from capacitor mismatches, finite Operational Transconductance Amplifier (OTA) gain and OTA´s settling error. This calibration method is based on radix-based calibration, and Pseudo-random Noise (PN) sequence is injected into the Multiplying DAC (MDAC) to extract the equivalent radix. According to the calibration system, simulation results show that when the prototype ADC is sampled at 125 MS/s, the Spurious Free Dynamic Range (SFDR) improves from 51.64 dB to 102.27 dB with calibration, and the Signal to Noise and Distortion Ratio (SNDR) improves from 36.47 dB to 80.86 dB with calibration.

Keywords

analogue-digital conversion; calibration; capacitors; operational amplifiers; OTA gain; OTA settling error; PN dithering; calibration system; capacitor mismatch; digital calibration technique; equivalent radix; finite operational transconductance amplifier; linearity error; multiplying DAC; noise figure 36.47 dB to 102.27 dB; pipelined ADC; pseudo-random noise sequence; radix-based calibration; spurious free dynamic range; word length 14 bit; Pseudo-random Noise (PN) sequence; digital calibration; pipelined ADC; radix-based calibration;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Signal Processing and Communications Systems (ISPACS), 2011 International Symposium on

Conference_Location

Chiang Mai

Print_ISBN

978-1-4577-2165-6

Type

conf

DOI

10.1109/ISPACS.2011.6146082

Filename

6146082