Process induced Wafer Geometry impact on center and edge lithography performance for sub 2X nm nodes

The change to vertical NAND will make the process complexity increase in traditional steps for example high temperature furnace processing, film deposition using CVD, CMP to planarize the deposited film, film etching, wafer bevel and backside processing. With these significant changes in complexity, wafer topology will get worse and less stable. Our current methodology and technique to detect problems caused by wafer topology need a better metric to represent line performance. In this paper we will propose a new method using Patterned Wafer Geometry (PWG) tool to measure and detect wafer topology changes inline. This method will be compared to traditional methods like thickness measurement, defect scan, and probe data. PWG metrics were proven to predict yield or defect problem caused by wafer topology roll off, especially at the edge of the wafer. These metrics are capable of detecting intra-field topology change as well as wafer-to-wafer topology fluctuation. This new technique has the advantage of higher sampling rate and potential feed forward capability to stabilize inline performance.