• DocumentCode
    3246017
  • Title

    Parallel resonant DC link circuit-a novel zero switching loss topology with minimum voltage stresses

  • Author

    He, Jin ; Mohan, Ned

  • Author_Institution
    Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
  • fYear
    1989
  • fDate
    26-29 Jun 1989
  • Firstpage
    1006
  • Abstract
    A parallel-resonant DC link (PRDCL) circuit topology is presented as a way to realizing zero-switching-loss, DC-AC high switching frequency power conversion. The circuit is used as an interface between DC voltage supply and the voltage-source PWM (pulse-width-modulated) inverter. It provides a short zero-voltage period in the DC link of the inverter to allow zero-voltage switching to take place in the PWM inverter. The peak voltage stress on the PWM inverter switches is limited to the DC supply voltage. Another significant advantage of the proposed circuit is that the inverter can be controlled by the conventional PWM strategy. The circuit is systematically analyzed, and its operation principle is explained in detail. Design considerations and formulae are also presented. A complete zero-voltage-switching DC-AC converter system consisting of the proposed circuit and the PWM inverter is simulated on computer
  • Keywords
    losses; power convertors; switching; DC link circuit; DC-AC converter; PWM; VSI; circuit analysis computing; circuit topology; high switching frequency; parallel resonant power convertors; voltage source invertor; voltage stresses; zero switching loss; zero-voltage switching; Circuit topology; Power conversion; Pulse circuits; Pulse inverters; Pulse width modulation inverters; RLC circuits; Resonance; Switching frequency; Switching loss; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Electronics Specialists Conference, 1989. PESC '89 Record., 20th Annual IEEE
  • Conference_Location
    Milwaukee, WI
  • Type

    conf

  • DOI
    10.1109/PESC.1989.48589
  • Filename
    48589