DocumentCode
3246233
Title
On-line error detection and correction techniques for TSV in three-dimensional integrated circuit
Author
Cheng, Chang-Hsin ; Liu, Chung-Kai ; Liu, Hsing-Chuang ; Ji, Kung-Ming
Author_Institution
Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
fYear
2011
fDate
7-9 Dec. 2011
Firstpage
1
Lastpage
5
Abstract
This paper presents an on-line error detection and correction techniques for through silicon via (TSV) in three-dimensional integrated circuit (3-D IC). The proposed architecture is based on biresidue codes to detect and correct the error on-line in the failed TSV over syndrome analysis. Experimental results show the proposed design has good performance in area and TSV overhead and improves the yield of TSV up to 99.9%.
Keywords
error correction; error detection; three-dimensional integrated circuits; TSV; biresidue code; on-line error correction technique; on-line error detection technique; syndrome analysis; three-dimensional integrated circuit; through silicon via; Computer architecture; Integrated circuits; 3-D IC; TSV; error correction; error detection;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Signal Processing and Communications Systems (ISPACS), 2011 International Symposium on
Conference_Location
Chiang Mai
Print_ISBN
978-1-4577-2165-6
Type
conf
DOI
10.1109/ISPACS.2011.6146105
Filename
6146105
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