DocumentCode
3246238
Title
Composite attribute method and software to interlock semiconductor product design and manufacturing yield
Author
Bickford, Jeanne P. ; Rolfing, Lori ; Sullivan, Candance ; They, Carlos ; Wolf, Edward M. ; Yoder, Joseph W. ; Niekrewicz, Paul
Author_Institution
Custom Logic, IBM Syst. & Technol. Group, Essex Junction, VT, USA
fYear
2015
fDate
3-6 May 2015
Firstpage
416
Lastpage
420
Abstract
Semiconductor product design content changes in recent technology nodes significantly changes yield even when the same die size is maintained. A method and software has been developed and implemented in IBM´s 32 and 14nm ASIC products to track yield impacts related to content change throughout the design process so that unexpected cost impacts can be avoided.
Keywords
application specific integrated circuits; integrated circuit yield; IBM ASIC products; composite attribute method; interlock semiconductor product design; manufacturing yield; size 14 nm; size 32 nm; yield impacts; Circuit faults; Libraries; Logic gates; Manufacturing; Product design; Redundancy; Yield estimation; circuit content; design changes; yield;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference (ASMC), 2015 26th Annual SEMI
Conference_Location
Saratoga Springs, NY
Type
conf
DOI
10.1109/ASMC.2015.7164432
Filename
7164432
Link To Document