A Low-Power Low-Voltage CMOS Thyristor Based Delay Element

A new low power low voltage CMOS thyristor delay element is proposed in this paper. The delay range of the proposed circuit is extended by reducing charge sharing problem. The delay element has less voltage and temperature sensitivity and consumes less power. The circuit is implemented in 130 nm technology and simulation result shows that the delay range is from 180 ps to 9 ns which is very high compared to other architectures of CMOS thyristor delay element. The power consumption is in the range of 24 ¿W to 243 ¿W. This circuit also has low voltage and temperature sensitivity compared to previous circuits. A digitally controlled current source is implemented to generate control current in the range of 1 ¿A to 32 ¿A. A cascode current mirror is used to couple the control current to the delay element circuit.