Collapse-free patterning of high aspect ratio silicon structures for 20nm NAND Flash technology

In this paper, the observation of active area line collapse in 20 nm planar NAND Flash technology is reported. The mechanism of active area pattern collapse is described using the theory of capillary forces. The proposed model for pattern collapse is validated by data obtained by real time defect analysis and end of line electrical data. Next, with the help of an empirical model, key structural metrics responsible for pattern collapse phenomenon are identified and optimized. The results from the optimized process flow show an 84% reduction in pattern collapse defects and 34% reduction in program disturb fails.