• DocumentCode
    3247097
  • Title

    Integrated interconnect circuit modeling for VLSI design

  • Author

    Jung, Won-Young ; Cha, Ghun-Up ; Kim, Young-Bae ; Baek, Jun-Ho ; Kim, Choon-Kyung

  • Author_Institution
    LG Semicon Co. Ltd., Seoul, South Korea
  • fYear
    1995
  • fDate
    29 Aug-1 Sep 1995
  • Firstpage
    165
  • Lastpage
    169
  • Abstract
    An integrated interconnect modelling system, SIMS, is developed with parametrized modeling of interconnect and an interface with schematic capture and editor. SIMS automatically drives numerical interconnect simulation as directed by technology engineers, creates a polynomial model library for interconnect parasitics, generates a netlist including the SPICE model for the interconnect structure, automatically drives circuit simulations and displays the simulation results through an advanced GUI. VLSI design with SIMS makes it possible to consider parasitic effects fast and accurately, which becomes more important in deep submicron circuit design. With this capability, circuit design with optimized interconnect layout can be achieved. Ultimately, the integrated system helps to reduce the cost of technology development and the time to market by building up the concept of design for manufacturability
  • Keywords
    SPICE; VLSI; circuit analysis computing; integrated circuit design; SIMS; SPICE Interconnect Modeling System; SPICE model; VLSI design; advanced GUI; circuit simulations; deep submicron circuit design; design for manufacturability; integrated interconnect circuit modeling; interconnect parasitics; netlist; numerical interconnect simulation; optimized interconnect layout; parametrized modeling; parasitic effects; polynomial model library; schematic capture; technology development; technology engineers; time to market; Circuit simulation; Circuit synthesis; Drives; Integrated circuit interconnections; Integrated circuit technology; Libraries; Numerical simulation; Polynomials; SPICE; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
  • Conference_Location
    Chiba
  • Print_ISBN
    4-930813-67-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.1995.486218
  • Filename
    486218