A digital audio signal processor for cellular phone application

A salient digital audio signal processor for a mobile communication receiver is described. With this IC, the complete audio signal processing system of an AMPS or a TACS cellular phone is easily implemented. The processor can be also applied to cellular radio, high performance cordless telephone, etc. In the paper, as an example of application, the implementation of the AMPS audio signal processing system is presented. To save power consumption, some special consideration of low power architectures has been made. The DSP core uses 4 stage pipelining without a routine memory access stage to reduce the power consumption and execution speed. The parallel calculations of data in the DSP and separated filter blocks also contribute to reduce the clock frequency and to save power. It also provides a power-down mode that turns off the IC except the internal bus interface in the standby mode. It uses a 3.3 V power supply, a 10 MHz 4-phase clock. The data sampling rate is 10 K-samples per second