Title :
A three-layer over-the-cell multi-channel routing method for a new cell model
Author :
Tsuchiya, Masahiro ; Koide, Tetsushi ; Wakabayashi, Shinichi ; Yoshida, Noriyoshi
Author_Institution :
Fac. of Eng., Hiroshima Univ., Japan
fDate :
29 Aug-1 Sep 1995
Abstract :
We present a new cell model for over-the-cell routing and a new over-the cell multi-channel routing method. In the proposed new cell model, terminals can be placed arbitrarily on the second layer of a cell so that each cell does not require the extra routing region on the first layer of a cell to align terminals. Unlike conventional cell models, some parts of the second layer are also utilized for the intra-cell routing in order to reduce the chip area. Therefore the size of the proposed cell model can be smaller than that of a conventional cell model. The proposed method consists of three phases. In order to utilize the proposed cell model, in phase 1, we simultaneously handle all channels to determine the most effective routing patterns from the set of possible routing patterns to minimize the chip area. In phase 2, for the effective routing patterns of nets selected in phase 1, over-the-cell routing nets are selected by a new greedy algorithm considering obstacles on over-the-cells. Finally, the conventional channel routing algorithm is applied for nets unrouted on over-the-cell. From the experimental results with MCNC benchmarks, the proposed cell model and algorithm produce smaller height of layouts as compared to those produced by conventional cell models and algorithms, and the effectiveness of the proposed method and cell model was shown
Keywords :
circuit layout CAD; circuit optimisation; directed graphs; integer programming; integrated circuit layout; network routing; performance evaluation; MCNC benchmarks; cell model; channel routing algorithm; chip area; circuit routing; directed graphs; experimental results; greedy algorithm; integer programming; intra-cell routing; routing patterns; terminals; three-layer over-the-cell multichannel routing; Algorithm design and analysis; Cities and towns; Electronic mail; Heuristic algorithms; Linear programming; Routing; Standards development; Testing;
Conference_Titel :
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
Conference_Location :
Chiba
Print_ISBN :
4-930813-67-0
DOI :
10.1109/ASPDAC.1995.486223